Receiver circuits, like serializer/deserializer (SERDES) circuits, are becoming ubiquitous in many computational environments. The SERDES can compress a relatively wide, parallel input into a relatively narrow, serial signal (e.g., a single “bit,” differential signal) for communication over a serial bus. The serial bus switches at an appreciably higher rate than the parallel bus, and serial communication of the data stream tends to reduce cost, complexity, power, and board real estate relative to comparable parallel communications. As bus speeds increase, parallel communications manifest even higher power consumption and more issues relating to timing (e.g., skew mismatches and bit misalignment), making SERDES circuits even more attractive.
Often, the receiver circuits include various sub-circuits that attempt to reliably extract digital data from a received signal, which can involve sampling an analog signal to derive the digital bits (i.e., ‘1’s and ‘0’s). Accurate sampling can rely on determining where bit transitions occur and what bit value to record, even in context of noisy data, small signal levels, inter-symbol interference (ISI), and other difficult conditions. Over time, these and other conditions in the receiver circuits (e.g., and potentially also with their respective transmitter circuits, data channels, etc.) can contribute to bit errors in decoding the received signal, which can manifest as a degradation in link health. Accordingly, receiver circuits typically include various types of sub-circuits for reducing such bit errors, such as amplifiers, analog to digital conversion sub-circuits (e.g., data slicers), clock data recovery sub-circuits (e.g., error slicers), equalizer sub-circuits, etc. Some equalizer sub-circuits are decision feedback equalization (DFE) circuits, which can use a knowledge of previously received symbols to cancel ISI on the data channel. However, many conventional DFE approaches are too slow (e.g., have too much latency) and/or too expensive (e.g., consume too much power and/or area) to be implemented effectively for very high-speed links (e.g., at Gigabit-per-second and higher data rates).